The semiconductor industry is rapidly developing chips with smaller and smaller transistor dimensions to gain more functionality per unit area. As the dimensions of devices continue to shrink, so does the gap/space between the devices, increasing the difficulty to physically isolate the devices from one another. Filling in the high aspect ratio trenches/spaces/gaps between devices which are often irregularly shaped with high-quality dielectric materials is becoming an increasing challenge to implementation with existing methods including gapfill, hardmasks and spacer applications.
Resistance-Capacitance (RC) delay is a challenging aspect of back end of line (BEOL) device production. The RC delay continues to increase with metal pitch scaling, metal line length increasing and metal line thickness decreasing. Reducing metal line resistance or dielectric capacitance in the back end of line is a priority of engineers working on BEOL. Low dielectric constant (k) materials are the main materials besides metals in the BEOL, which account for the capacitance that needs to be reduced. Reducing k has been a trend in the past decades. IBM introduced the air-gap technology around 10 years ago. However, it has not penetrated in the whole industry because of the process/design/integration complexity.
Another challenging aspect in the current semiconductor manufacture is edge placement error (EPE) appearing in the patterning steps. When patterning multiple layers, layer-to-layer connection or alignment becomes more and more difficult with smaller features. On BEOL, big EPE could cause both the resistance of interconnect and parasitic capacitance to increase which will increase the RC delay. In the worst cases, the EPE can result in the misalignment of two metal layers and device failure.
Therefore, there is a need in the art for methods for back end of line device production with decreased RC delay and/or decreased edge placement error.